000			01202nam a22003377a 4500
001			NM000899
003			AR-HaUTN
007			ta
008			48020s2007 ||||||||||||||000 | spa||
005			20240930172056.0
040			_aAR-HaUTN
245			_aIntel 64 and IA32 architectures _boptimization reference manual
260			_aDenver _bIntel
300			_aca. 450 p. _bcuadros, gráficos
500			_aIndice alfabético, al final del libro
505			_tIntel 64 and IA 32 processor architecture
505			_tGeneral optimization guidelines
505			_tCoding for SIMD architectures
505			_tOptimizing for SIMD integer applications
505			_tOptimizing for SIMD floatingpoint applications
505			_tOptimizing cache usage
505			_tMulticore and Hyperthreading technology
505			_t64bit mode coding guidelines
505			_tPower optimization for mobile usages
505			_tApplication performance tools [ppendix A]
505			_tUsing performance monitorin events [Appendix B]
505			_tInstruction latency and throughput [Appendix C]
505			_tStack alignment [Appendix D]
505			_tSummary of rules and suggestions [Appendix E]
942			_cBK
999			_c899 _d899